| 摘要 |
PROBLEM TO BE SOLVED: To reduce the skew between wirings with a high accuracy by calculating the output delay, based on cell information of a plurality of kinds of clock drivers having different drive powers but the same overall dimensions, the same pin layout and the same input capacitance on layout data and allowing the output delay value to be change to another delay according to the change of parameters on a static/dynamic delay verifying tool. SOLUTION: The output delay of clock drivers are calculated by a delay value calculating tool from cell delay information 102 of the four clock drivers and layout data 101 after the layout and wiring when prepared clock drivers A-D are disposed by a delay extracting tool 103 for nodes of the clock drivers, and separately stored in individual files 105-110. The output delay value of each clock driver generated by the processing is parameterized on a dynamic delay verifying tool wherein the delay values of nodes of other devices than the clock drivers are stored in a separate file 104.
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