| 摘要 |
PROBLEM TO BE SOLVED: To make a circuit scale of the generator small with a simple configuration by applying frequency division to a 1st clock obtained from 2nd video data at a prescribed frequency division ratio, in response to the format of the 2nd video data so as to generate a 2nd clock and reading 1st video data based on the 2nd clock. SOLUTION: A horizontal frequency divider 50 and a vertical frequency divider 51 in each of OSD pattern detection circuits 41-43 apply frequency division to each dot clock Dcl of horizontal address data Dha and vertical address data Dva respectively at a prescribed frequency division ratio, based on a frequency division ratio setting signal SFD received from a CLU to respectively adjust the scanning timing of the horizontal address data Dha and the vertical address data Dva. Then the OSD pattern read circuits 41-43 supply horizontal read address data D1h-D3h and vertical address data D1v-D3v to an OSD plane memory so as to supply sequentially addresses in a horizontal direction and in a vertical direction of a bit map in a memory.
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