| 摘要 |
<p>A dummy fill pattern for a multi-layer semiconductor device is based upon an intelligently designed dummy fill cell. The dummy fill pattern is formed from an array of the dummy fill cells. The dummy fill cell is configured to reduce the amount of undesirable layer-to-layer interaction, e.g., capacitance, between different material layers within the semiconductor device. The dummy fill cell includes regions associated with each of the material layers that include dummy fill. For example, a region of the dummy fill cell may be associated with a metal-1 layer and a separate region of the cell may be associated with a metal-2 layer. The configuration of the different regions is such that the likelihood of layer-to-layer interactions is reduced. In addition, the dummy fill pattern itself may be intelligently designed to contemplate possible layer-to-layer effects. The dummy fill pattern for a first material layer may be suitably designed such that the dummy fill of the first material layer does not reside above the circuit pattern for the underlying layer. Similarly, the dummy fill of the first material layer may be configured such that it does not lie below the circuit pattern for the abovelying layer.</p> |
