VSB RECEIVER

摘要

A loop gain of an AGC circuit (7) and a loop gain of a clock regenerative circuit (6) are kept increased (an amplifier gain is increased or a loop filter is set to a wide band) until a synchronizing signal (a segment synchronizing signal or field synchronizing signal) is detected. After a synchronizing signal is detected, a loop gain of the AGC circuit (7) and a loop gain of the clock regenerative circuit (6) are reduced (an amplifier gain is decreased or the loop filter is set to a narrow band). The above arrangements can make compatible the shortening of time required for completing a converging processing in the AGC circuit and the clock regenerative circuit with the increasing of ghost interference removal and an accurate clock regeneration.