LAYOUT OF A SEMICONDUCTOR MEMORY DEVICE

摘要

PURPOSE: A layout is provided to reduce a load of input/output wiring and a chip size by arranging global input/output wiring at the center of memory cell blocks. CONSTITUTION: A layout comprises: plural memory cell blocks(MAT) including plural memory cells; plural sense amplifier blocks(SA) having plural sense amplifiers; plural sub word line drivers(SWD); global input/output lines(Global IO) arranged over the memory cell blocks(MAT) and the sense amplifier blocks(SA) to form a strap portion; and local input/output lines(Local IO) crossed with the global input/output lines(Global IO) and disposed over the sense amplifier blocks(SA), to thereby reduce a resistance of the local input/output lines(Global IO) for a signal stabilization.