INTEGRATED CIRCUIT COMPRISING VERTICAL TRANSISTORS, AND A METHOD FOR THE PRODUCTION THEREOF

摘要

The transistor is configured as a vertical MOS transistor and comprises a series of layers (SF, SF*) which is arranged on a substrate (1) doped with a first type of conductivity. Said series of layers has a lower layer (U) for a first source/drain region, a middle layer (M) which is doped with a first type of conductivity and which is provided for a channel region, and has an upper layer (O) for a second source/drain region. A connecting structure (V) which is doped with a first type of conductivity is arranged on at least one first surface of the series of layers (SF, SF*) in order to electrically connect the channel region to the substrate (1). A gate electrode of the transistor is arranged on at least one second surface of the series of layers (SF, SF*). The connecting structure (V) can be arranged between the series of layers (SF, SF*) and another series of layers (SF, SF*) which can belong to the same or another transistor. The dimensions of the connecting structure (V) and of the series of layers (SF, SF*) can be sublithographic. The production results in a self-adjusting manner. The circuit is suited as a storage cell arrangement having a high packing density.