发明名称 |
METHOD FOR MANUFACTURING GATE ELECTRODE USING POLYSILICON |
摘要 |
PURPOSE: A gate electrode fabrication method is provided to reduce a stress due to concentration differency of impurity distribution and prevent a lifting during tungsten silicide process by removing excess impurity doped region. CONSTITUTION: A gate electrode has laminated structure by sequentially depositing an undoped polysilicon(13) and a doped polysilicon(14). Then, annealing process is performed to reduce a resistance of the gate electrode and simultaneously formed a polysilicon layer(15) having an excess impurity doping region(16) at the top portion of the gate electrode. The excess impurity doping region(16) is then removed by plasma etching or CMP(chemical mechanical polishing), thereby improving a uniformity of doped impurity distribution.
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申请公布号 |
KR20000019154(A) |
申请公布日期 |
2000.04.06 |
申请号 |
KR19980037121 |
申请日期 |
1998.09.09 |
申请人 |
ANAM SEMICONDUCTOR., LTD. |
发明人 |
CHO, KYUNG SU |
分类号 |
H01L21/336;(IPC1-7):H01L21/336 |
主分类号 |
H01L21/336 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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