| 摘要 |
PURPOSE: A system clock board prevents the data breaking phenomenon of the whole system occurred in active/standby switching by constructing each board by including a phase detector and a frequency regulator. CONSTITUTION: A system clock board includes an active board(31) comprising: a first digital matching part outputting one clock by receiving external output clocks; a first PLL(34) synchronizing an internal clock to the output clock of the digital matching part; a first clock generation part(35) generating a system supply clock by receiving the synchronized internal clock; a first clock distribution part(36) outputting the system supply clock to the system; a first control part(37) controlling the output of the first clock generation part; a first phase detector(38); and a first frequency regulator(39), and a standby board(32) comprising: a second PLL(Phase locked loop) synchronizing an internal clock to the output clock of the second digital matching part; a second digital matching part receiving the output clock of the first clock distribution part; a second clock distribution pat outputting the system supply clock to the system; a second phase detector detecting the phase difference between the output clocks of the first and the second clock distribution parts; and a second frequency regulator correcting the phase difference of a signal outputted from the second phase detector.
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