Circuit device for providing a hierarchical row decoding in semiconductor memory devices

摘要

The invention relates to a circuit device for carrying out a hierarchic form of row decoding in semiconductor memory devices of the non-volatile type and comprising at least one matrix of memory cells (5) with sectors (3,4) organized into columns, wherein each sector has a specific group of local word lines (LWL) individually connected to a main word line (MWL) running through all of the matrix sectors which have rows in common. The device comprises a first transistor (M1) of the PMOS type having its conduction terminals connected, the one to the main word line (MWL) and the other to the local word line (LWL), and a second transistor (M3) of the NMOS type having its conduction terminals connected, the one to the local word line (LWL) and the other to a reference voltage (GND). <IMAGE>