Clock recovery scheme for data transmission systems

摘要

A digital data 10 and a receiver 18 for use in a digital data system are disclosed. The receiver unit includes a clock recovery filter or PLL 26 for determining the clock signal. The receiver separates at 20 the data and clock components of the signal to produce at a decision circuit 28 a data output which is correctly sequenced. A single device may incorporate a signal divider 20 a low pass filter 22, and a high pass filter 24. The high pass filter 24 may may suitably be incorporated in a TDM or FDM system. The pilot clock signal impressed upon the incoming data may be an optical pre-chirped signal or other pre-emphasis signal. The data system may use a non-return-to-zero format.