Cache memory control method in which information is buffered and address held in back-up buffer, based on bit signal output from comparators

摘要

The control method involves performing a first process in which information is read from the cache memory (31) or information buffers (421-424) and supplied to the processor, if a bit signal is output from comparators (343-3410), or if no bit signal is output, a tag is read from tag memories (321,322) and temporarily held in tag buffers (351,352). In a second process, if a bit signal is output from the comparators, information is read from the cache memory and supplied to the processor. If no bit signal is output, the information is read from a main memory device based on an address signal (AD), temporarily held in the information buffers and cache memory, and the address of the information held in the information buffers is stored in a back-up buffer (39). Independent claims are included for; (1) a cache memory control method, and (2) a cache memory control device.