| 摘要 |
Sub-cell arrays are formed in p-type cell-forming wells, respectively, with a region between two adjacent sub-cell arrays being formed a sense amplifier circuit region which includes three wells, a first p-type well isolated from the p-type cell-forming wells, and first and second n-type wells for isolating the p-type cell-forming wells, wherein an NMOS sense amplifier is arranged in the first p-type well, a PMOS sense amplifier and a first switch circuit are arrange in one of the first and second n-type wells and a bit line equalizer circuit and a second switch circuit are arranged in the other of the first and second n-type well.
|
