| 摘要 |
Using positive-phase or negative-phase clocks of phase count clock Pf0, a number M of multilevel quantized phase comparators output as values quantized in multiple levels the phase differences of output signals outputted from first and second N-stage frequency dividers wherein input clocks and output clocks, respectively, of a digital PLL have been Nstage frequency divided and moreover, divided into M groups. An adder adds this phase difference information and outputs advanced pulses or delayed pulses. An N1 counter counts up in response to advanced pulses and both outputs an increment pulse and undergoes setting to initial value N1 upon counting up to 2N1. In response to delayed pulses, the N1 counter counts down, and upon counting down to "0" both outputs a decrement pulse and undergoes setting to initial value N1.
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