发明名称 Semiconductor memory device with multiplied internal clock
摘要 The practical operation speed of the memory device is increased by multiplexing input and output signals so as to increase the internal operation frequency higher than the external clock frequency. The feature of the memory device of the present invention is that it has the function of making the internal operation frequency higher than the external clock frequency by making the external bit width larger than the internal bit width, writing write data by dividing them successively by time division operation, into those having an internal bit width, and allocating read data to use an entire external bit width. According to the present invention, the practical operation speed of the memory device assembled on the board can be increased over the upper frequency limit of signals transmitted through the wiring on the board, and the high frequency performance of the memory device can be tested at the step of the die sorting test.
申请公布号 US6047344(A) 申请公布日期 2000.04.04
申请号 US19980034218 申请日期 1998.03.04
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 KAWASUMI, ATSUSHI;MIYANO, SHINJI
分类号 G11C11/41;G11C7/22;G11C11/401;G11C11/407;G11C29/56;(IPC1-7):G06F13/42;G06F12/00;H04L7/00 主分类号 G11C11/41
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