| 摘要 |
A voltage bias generator circuit which uses a series of small transistors to form essentially a resistor ladder to produce a desired bias voltage at an intermediate node using the sizing of the transistors and the placement of the node. The output node is then connected to a first voltage level shifting circuit for shifting the voltage by at least 1 VT. The output of the first voltage level shifting circuit is then coupled to the second voltage level shifting circuit, which shifts it back down or up to the desired bias voltage.
|
