发明名称
摘要 PURPOSE:To obtain the arithmetic processor of a programmable controller whose cost performance is high by decreasing the cost of a used memory, and executing the architecture of the arithmetic processor by which a pipe line execution with the high efficiency of an application command can be attained. CONSTITUTION:An arithmetic processor 1 is constituted of an instruction fetching unit part 2, control unit 3, bit processing unit part 4, multibit processing unit part 5, and data memory bus interface part 6. The pipe line execution of a frequently-used sequence command is operated by the bit processing unit part 4, and the pipe line execution of the application command for a data processing is operated by the multibit processing unit 5 after complied to an RISC type data processing command.
申请公布号 JP3027627(B2) 申请公布日期 2000.04.04
申请号 JP19910186628 申请日期 1991.07.25
申请人 发明人
分类号 G05B19/05;G05B19/048;G06F7/00;G06F9/32;G06F9/38 主分类号 G05B19/05
代理机构 代理人
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