发明名称 Method of fabricating a fabricating plug and near-zero overlap interconnect line
摘要 A method of fabricating an electrically conductive plug on a semiconductor workpiece. A dielectric layer is deposited on the workpiece, and a cavity is etched in the dielectric. An etchant-resistant material is deposited on the wall of the cavity adjacent the cavity mouth so as to form an inwardly-extending lateral protrusion, the etchant-resistant material being resistant to etching by at least one etchant substance which etches said electrically conductive material substantially faster than it etches the etchant resistant material. The cavity is filled by an electrically conductive material. In another aspect of the method, the etchant-resistant material can be omitted. Instead, upper and lower portions of the cavity are etched anisotropically and isotropically, respectively, so as to form a lower portion of the cavity that is wider than the upper portion. In a third aspect of the method, a higher density upper layer of dielectric is deposited over a lower density lower layer of dielectric. The two layers are etched to form a cavity. Because of the upper layer's higher density, it etches more slowly than the lower layer, producing a cavity having an upper portion that is narrower than its lower portion.
申请公布号 US6046100(A) 申请公布日期 2000.04.04
申请号 US19960762868 申请日期 1996.12.12
申请人 APPLIED MATERIALS, INC. 发明人 RAMASWAMI, SESHADRI;NULMAN, JAIM
分类号 H01L21/28;H01L21/768;H01L23/522;(IPC1-7):H01L21/311 主分类号 H01L21/28
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