发明名称 |
Process of testing integrated circuit dies on a wafer |
摘要 |
A semiconductor wafer has integrated circuit dies formed in an array of rows and columns. Selector circuits occur in the areas between the dies and are electrically connected to the individual dies for selecting between a functional mode and a bypass mode for testing. Probe areas are formed on the periphery of the wafer for accepting probe pins without contacting the bond pads of the dies. The dies and selector circuits are electrically connected to the probe areas for conducting electrical testing of the dies. The testing occurs by selecting only one die in a particular row and column and maintaining the remaining dies in a standby mode.
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申请公布号 |
US6046600(A) |
申请公布日期 |
2000.04.04 |
申请号 |
US19960741497 |
申请日期 |
1996.10.31 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
WHETSEL, LEE D. |
分类号 |
G01R31/317;G01R31/3185;(IPC1-7):G01R31/02 |
主分类号 |
G01R31/317 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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