发明名称 SEMICONDUCTOR DEVICE AND INSPECTION METHOD THEREOF
摘要 <p>PROBLEM TO BE SOLVED: To set pre-charge voltage arbitrarily and accurately by setting the pre-charge voltage of two bit lines at values lower than the intermediate voltage of the bit-line voltage amplitude of the two bit lines by adjusting a reference voltage value. SOLUTION: Voltage lowered by a threshold-voltage section from power- supply voltage VDD is supplied by using an N channel MOS transistor Qm1, in which a drain and a gate are connected to VDD. (FB3, FB2, FB1, FB0)=(H, L, H, L) is programmed by a VBP reference-voltage setting circuit 34 for a VBP generating circuit 12c. Since the on resistance of transistors Tm1-Tm8 is made sufficiently lower than that of transistors Qr1-Qr8 connected in parallel, resistance components composed of a P channel MOS transistor can be represented by the series resistance of Qr2, Qr4, Qr5 and resistance components constituted of the N channel MOS transistor represented by the series resistance of Qr6, Qr8, Qr10, and output voltage VREF is determined at the ratio of these resistance.</p>
申请公布号 JP2000090669(A) 申请公布日期 2000.03.31
申请号 JP19980252649 申请日期 1998.09.07
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SHIMAKAWA KAZUHIKO;ORIGASA KENICHI;OTA KIYOTO
分类号 G11C11/409;G11C11/401;G11C11/407;G11C16/02;(IPC1-7):G11C11/409 主分类号 G11C11/409
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