| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a timer circuit capable of realizing the number of timers more than the number of vectors in a vector table stored in a CPU and reducing the load of the CPU. SOLUTION: When a decrement period generation circuit 106 generates a decrement signal, a timer control circuit 107 decreases the contents of a timer buffer, and at the time of detecting which timer buffer is turned to a time-out state, writes the buffer number of the timer buffer turned to the time-out state in a time-out buffer 108 and a timer buffer clear circuit 109. When a CPU 101 reads out the contents of the buffer 108, the circuit 109 turns the timer buffer corresponding to the stored buffer number to an operation stop state.</p> |
