| 摘要 |
PROBLEM TO BE SOLVED: To enable high-speed operation by connecting a first pre-charge transistor having large gate width and a second pre-charge transistor having small gate width in parallel among a digit line pair and a power supply when data are read to the digit line pair from a memory cell. SOLUTION: P channel transistors 6, 7 represent transistors for large pre- charge and P channel transistors 8, 9 transistors for small pre-charge, and the transistors 6, 7 have large gate width and conduct the pre-charge operation of a digit. When the control signal 10a of a signal conductor 10 for controlling pre-charge/equalize reaches a low level, P channel transistors 5, 6, 7 turn on, and conduct the equalize and pre-charge of a digit line. The gate potential of the P channel transistors 8, 9 having small gate width is controlled by a signal by the combination of the precharge/equalize control signal 10a and a read control signal 14.
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