| 摘要 |
PROBLEM TO BE SOLVED: To provide a synchronous circuit capable of surely matching the phase of frequency signals to be a clock with the phase of binary digital signals such as input data signals without the need of pre-adjustment. SOLUTION: By D latches 11 and 12, clock signals are respectively latched by the signals of the positive phase and opposite phase of the input data signals. Among them, the clock signal in a latched state is selectively outputted by a selector 13, the output signal is supplied through an LPF 15 to a voltage controlled oscillator 18 to constitute a PLL, thus the phase of the clock signals outputted from the voltage controlled oscillator 18 is controlled. |
