| 摘要 |
PROBLEM TO BE SOLVED: To conduct test of DRAM with a less number of input/output pins and simultaneously test a larger number of LSIs. SOLUTION: This test circuit is composed of two pins to which a data mode input signal and a data pattern input signal are respectively input from external circuits, a data generating circuit 4 for generating the test data DI<7:0> based on these two input signals, a data comparing circuit 5 for comparing the data DO<7:0> which is read after the data DI<7:0> is stored in DRAM 2 and its expectation value, a data comparison result output signal indicating the comparison result and two pins for externally outputting the data pattern output signal consisting of the value DO<0> of 0th bit of the data DO<7:0>.
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