发明名称 |
Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device |
摘要 |
A memory device is described which has an n-channel field effect transistor coupled between a memory cell and a data communication line. An NPN bipolar junction transistor is also coupled between the memory cell and the data communication line in parallel to the n-channel access transistor. A base connection of the NPN bipolar junction transistor is described as coupled to a body of the n-channel access transistor. During operation the n-channel field effect transistor is used for writing data to a memory cell, while the NPN bipolar junction transistor is used for read operations in conjunction with a current sense amplifier circuit. The access transistors are described as fabricated as a single vertical pillar.
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申请公布号 |
US6043527(A) |
申请公布日期 |
2000.03.28 |
申请号 |
US19980060048 |
申请日期 |
1998.04.14 |
申请人 |
MICRON TECHNOLOGY, INC. |
发明人 |
FORBES, LEONARD |
分类号 |
G11C8/16;G11C11/404;G11C11/405;H01L27/06;H01L27/108;(IPC1-7):H01L27/108;H01L29/16;H01L29/94;H01L31/119 |
主分类号 |
G11C8/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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