| 摘要 |
The present invention provides a voltage level shifter for use in a digital circuit having a low voltage portion and a high voltage portion. The voltage shifter comprises an interface circuit 20,32,60 that senses transitions in a low voltage digital signal from an old value to a new value and uses these to trigger latching of the new value. The latch can be a SR latch 34,62 with its set 40 and reset 42 inputs coupled to pulse generators 46,68,58,70 respectively responsive to rising and falling edges in the input low voltage signal being passed from the low voltage portion to the high voltage portion. Feedback from the output on the latch 62 can be controlled to limit the duration of the pulses from the pulse generators 68,70 and thereby reduce power consumption due to the dc current leakage associated with a low voltage to high voltage signal interface.
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