| 摘要 |
A calibrated Delay Locked Loop (DLL) arrangement synchronizes an output data signal thereof to an input clock signal. A delay line receives the input clock signal and generates a clock output signal having a selective delay. A gating circuit receives the clock output signal and separately generates an imitation data signal that corresponds to the clock output signal, and latches an input data signal with the output clock signal to generate an output data signal. The gating circuit is also responsive to a switching control signal having a first logical value for providing only the output data signal to an output thereof, and to the switching control signal having a second logical value for providing only the imitation data signal to an output thereof. A driver receives the gating circuit output signal and provides this signal as the calibrated DLL arrangement output data signal. A phase comparator in a feedback loop from the output of the driver is responsive to the switching control signal having the second logical value for comparing the input clock signal and the imitation data signal appearing at the driver output, and for causing the delay line to selectively synchronize the imitation data signal to the input clock signal. A switching control signal having the first logical value idles the phase comparator and maintains a latest delay introduced by the delay line.
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