| 摘要 |
A level shift circuit reduced in a circuit area and conversion delay when converting a signal level, capable of operating at a high speed, expanded in the range of the operatable voltage, and capable of operating at a low voltage, including a first transistor connected between a voltage Va source and an output terminal, a second transistor connected between a voltage Vc source and an output terminal, a third transistor connected between a voltage Vc source and a gate of the second transistor, a fourth transistor connected between a voltage Va source and the gate of the second transistor, a fifth transistor connected between the ground and the output terminal, and a sixth transistor connected between the ground and the gate of the second transistor, wherein a connection point of an output terminal and the first, second, and fifth transistors is connected to a gate of the third transistor, gates of the fourth and fifth transistors are connected to an input terminal, and an inverted signal of an input signal to the input terminal is supplied to gates of the first and sixth transistors.
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