| 摘要 |
A clock distribution system is described for providing synchronous clock signals in as many phases as a designer of a given circuit finds useful. The clock distribution system acknowledges timing constraints of the controlled system, and adjusts the clock phase appropriately to meet the needs of the local data circuits using the clock signals. The clock distribution system includes stages which are coupled to appropriate portions of the datapath and to each other for controlling the datapath and provide information about clock signal timing to each other. |
