发明名称 |
INTEGRATED CIRCUIT HAVING HORIZONTALLY AND VERTICALLY OFFSET INTERCONNECT LINES |
摘要 |
<p>PURPOSE: An improved multilevel interconnect structure is provided. CONSTITUTION: An interconnect structure includes several levels of conductors, wherein conductors on one level are staggered with respect to conductors on another level. Accordingly, a space between conductors on one level is directly above or directly below a conductor within another level. The staggered interconnect lines are advantageously used in densely spaced regions to reduce the interlevel and intralevel capacitance. An interlevel and an intralevel dielectric structure includes optimally placed low K dielectrics which exist in critical spaced areas to minimize capacitive coupling and propagation delay problems. The low K dielectric includes a capping dielectric which is used to prevent corrosion on adjacent metallic conductors, and serves as an etch stop when conductors are patterned. The capping dielectric further minimizes the overall intrinsic stress of the resulting intralevel and interlevel dielectric structure.</p> |
申请公布号 |
KR20000016077(A) |
申请公布日期 |
2000.03.25 |
申请号 |
KR19987009644 |
申请日期 |
1998.11.27 |
申请人 |
ADVANCED MICRO DEVICES INC |
发明人 |
BANDYOPADHYAY BASAB;BRENNAN WILLIAM S;DAWSON ROBERT;HAUSE FRED N;MICHAEL MARK W;FULFORD JR H JIM |
分类号 |
H01L21/302;H01L21/3065;H01L21/312;H01L21/3205;H01L21/768;H01L21/822;H01L23/52;H01L23/522;H01L23/528;H01L27/04;(IPC1-7):H01L23/522 |
主分类号 |
H01L21/302 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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