发明名称 TRIGGERED CLOCK SIGNAL GENERATOR
摘要 A triggered clock signal generator (10) produces a periodic output clock signal (CLOCK3) in response to an input TRIGGER signal, wherein a delay between the TRIGGER signal and the first pulse of the CLOCK3 signal is accurately adjustable. The apparatus includes a period generator (12) and a phase adjuster (14). The period generator (12), using a periodic input signal (CLOCK1) as a timing reference, responds to the TRIGGER signal by producing a periodic output clock signal (CLOCK2) in adjustably delayed response to a next pulse of the CLOCK1 signal. The phase adjuster phase shifts (18) the CLOCK2 signal to produce to CLOCK3 signal. The phase adjuster compares (16) the phase of the CLOCK1 signal to the phase of the TRIGGER signal to determine an appropriate amount by which to phase shift the CLOCK2 signal so that the time delay between the TRIGGER signal and the first pulse of the CLOCK3 signal is independent of the phase relation between the TRIGGER and CLOCK1 signals.
申请公布号 WO0016515(A1) 申请公布日期 2000.03.23
申请号 WO1999US21010 申请日期 1999.09.14
申请人 CREDENCE SYSTEMS CORPORATION 发明人 DINTEMAN, BRYAN, J.
分类号 G06F1/06;G01R31/30;G06F1/04;G06F1/08;H03L7/00;H03L7/081;(IPC1-7):H04L7/00;H04L23/00 主分类号 G06F1/06
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