| 摘要 |
A microprocessor configured to predict the length of variable length instructions for decoding purposes by detecting patterns of instruction lengths that have been previously decoded. The microprocessor has a cache, an instruction length calculation unit, and a pattern detector. The instruction length calculation unit receives instruction bytes from the cache and generates an instruction length corresponding thereto. The pattern detector stores a plurality of instruction length sequences, each comprising an initial sequence and a final sequence. The pattern detector is configured to receive instruction lengths from the length calculation unit and compare them with the stored initial sequences. If the pattern detector finds a match, it outputs the corresponding final sequence for use as predicted instruction lengths. A method for using instruction length pattern detection for decoding is also disclosed.
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