| 摘要 |
The semiconductor memory device comprises a memory array (9) and a data bus line (1) for transferring read and write data between the memory array and an input buffer (IB) and an output buffer (OB) and also transferring an information indicating read or write mode operation. The data bus line transfers the read data as a complement signal having a predetermined amplitude which is smaller than a potential difference between high and low level power source lines (7 and 8, respectively). The predetermined amplitude is defined by a first and a second impedance (2 and 3, respectively) connected between the data bus line and a first and a second power source line (7 and 8), respectively, The first impedance (2) is associated with a first end of the data bus line in the input-output buffer area and the second impedance (3) is associated with a second end of the data bus line in the inner circuit area of the device. The write data is transferred via the data bus line (1) as a complement signal having a larger amplitude than that of read data. The memory array accepts the signal on the data bus line as a write data signal according to its amplitude. The memory array (9) is equipped with a write control gate for detecting the amplitude of the complement signal on the data bus lane (1).
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