发明名称 WRITE AND ERASE METHOD OF SEMICONDUCTOR MEMORY
摘要 PROBLEM TO BE SOLVED: To provide a write and erase method of a semiconductor memory which is free from lowering of write speed, enables single power supply and deteriorates less by repeated rewriting. SOLUTION: While electrons are stored in a floating gate electrode 5 by Fowler-Nordheim tunneling effect by applying a positive voltage to a control gate electrode 7 and applying a voltage which is lower than the positive voltage to a semiconductor board 1, a ground voltage or a negative voltage is applied to the control gate electrode 7 and a voltage which is higher than the voltage applied to the control gate electrode 7 to the semiconductor board 1. As a result, electrons stored in the floating gate electrode 5 are removed by a similar phenomenon.
申请公布号 JP2000082752(A) 申请公布日期 2000.03.21
申请号 JP19980252321 申请日期 1998.09.07
申请人 MATSUSHITA ELECTRONICS INDUSTRY CORP 发明人 SATO KAZUO
分类号 H01L21/8247;H01L27/115;H01L29/788;H01L29/792;(IPC1-7):H01L21/824 主分类号 H01L21/8247
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