| 摘要 |
PURPOSE:To obtain a burst lock PLL circuit of only one system in which a clock whose frequency is an integral multiple of two kinds of subcarrier frequencies whose phase is matched with the phase of a burst signal. CONSTITUTION:A frequency division phase control circuit 111 provided on a next-stage to a voltage controlled oscillator 107 matches the phase of a clock (fsc) of a subcarrier frequency with the phase of a clock (4fsc) resulting from 1/2-frequency dividing a 2n-multiple of clock (8fsc) of the subcarrier frequency for each frequency fsc. As a result, the phase of the subcarrier clock (fsc), a 2n-multiple clock (8fsc) of the subcarrier, a clock (4fsc) applying 1/2-frequency dividing a 2n-multiple clock of the subcarrier is in matching with the phase of a burst signal without fail to keep a stable phase lock state. |
