| 摘要 |
PROBLEM TO BE SOLVED: To realize a high speed operation, to execute a normal operation without being affected by the delay quantity in a delay circuit and to eliminate jitters in the permissible phase difference of an intra-chip clock by providing a phase comparison circuit outputting a phase synchronizing signal. SOLUTION: A delay circuit 101 outputs clocks delayed in respective gate circuit units from the output terminals of respective gate circuits. A phase comparison circuit 102 compares the phases of an intra-chip clock and a system clock and outputs L when the phase of the intra-chip proceeds as an up down counter control signal and outputs H when the phase is delayed. When the intra-chip clock is within the permissible phase difference, L is outputted as a phase synchronizing signal from a phase synchronizing signal output terminal 109 and H when it is out of the permissible phase difference. An up/down counter 103 outputs the count value of the up down counter control signal. A selection circuit 104 selects output corresponding to the count value and outputs it from the clock output terminal 108 of a phase locked loop.
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