| 摘要 |
A connection matrix for a microcontroller emulation chip, which comprises memory cells of the RAM type comprising: first and second MOS transistors connected in series with each other between first and second voltage references, and having their drain terminals in common to form a first internal circuit node; third and fourth MOS transistors, also connected in series with each other between the first and second voltage references, and having their drain terminals in common to form a second internal circuit node; wherein the first and second transistors have their control terminals connected together and to the second internal circuit node, and the third and fourth transistors have their control terminals connected together and to the first internal circuit node; and fifth and sixth MOS transistors, respectively connected between first and second input terminals of the RAM cell and the first and second internal circuit nodes, and having respective control terminals connected to a third input terminal of the RAM cell; further comprising at least one controlled switch connected between the first and second internal circuit nodes adapted to control the switch on/off, and provided with first and second connecting terminals between horizontal and vertical lines of the matrix.
|
