发明名称 |
DIGITAL PHASE LOCKED LOOP FREQUENCY SYNTHESIZER |
摘要 |
The invention relates to a circuit for phase error compensation in fractional-N-based phase locked loop frequency synthesizers. By means of said circuit all required control and reference signals are derived from the VCO frequency (fVCO) of the voltage-controlled oscillator (4) using an auxiliary phase locked loop (auxiliary PLL). The circuit provided for in the invention is suitable especially for high-frequency phase locked loop frequency synthesizers used in integrated circuit technology.
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申请公布号 |
WO0014879(A2) |
申请公布日期 |
2000.03.16 |
申请号 |
WO1999DE01569 |
申请日期 |
1999.05.28 |
申请人 |
SIEMENS AKTIENGESELLSCHAFT;GOSSMANN, TIMO;GOETZ, EDMUND |
发明人 |
GOSSMANN, TIMO;GOETZ, EDMUND |
分类号 |
H03L7/07;H03L7/081;H03L7/183;H03L7/197;(IPC1-7):H03L/ |
主分类号 |
H03L7/07 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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