Frequency divider for integrated circuit, generates output signal as exact fraction of input clock signal

摘要

The divider comprises several transmission units series-connected in a ring. At least one transmission unit is clocked by the frequency of the electric input signal, as it comprises an inverting logic circuit (31), whose output stage is clocked by at least one switch (32) incorporated in the load circuit, with the switch controlled by the input signal frequency. Preferably one clocked transmission unit contains a logic circuit in which both of the load circuit branches are clocked for positive and negative voltage by the input signal, or a signal derived by one by switches.