CLOCK PHASE COMPENSATING CIRCUIT

摘要

PURPOSE: A clock phase compensating circuit is provided to minimize a power consumption and a noise generation owing to a use of a turbo mode of a digital manner via a counter. CONSTITUTION: An amplifier part(10) amplifies an external clock(EX-CLK), and a reference clock generating part(20) receives an output from the amplifier part(10) to generate reference clocks. A phase mixer/control part(30) finely adjusts phases of the reference clocks in response to a phase detection signal(PD). A clock buffer(40) buffers an output from the phase mixer/control part(30) to generate an internal clock(IN-CLK). A phase detection control part(50) selects the internal clock or sequentially selects the reference clocks in response to an external turbo signal(EX-TB) and the phase detection signal(PD) to then output the selected signal as a phase detection control signal. A phase detection part(60) compares the external clock and the phase detection control signal to output the phase detection signal to the mixer/control part and to the phase detection control part(50).