| 摘要 |
<p>A phase-locked loop (PLL) frequency synthesizer includes a reference divider (RD) and PLL which has a phase/frequency divider (PFD), a charge pump (CP), a voltage control oscillator (VCO) and a feedback divider (FD). The RD's and FD's ratios R and N are varied. In a normal mode, the PFD and the CP cause the VCO frequency to be varied to be locked with a reference frequency. In a speed-up mode, both R and N are divided by the same factor M and the frequency of current generated by the CP is high, resulting in large average CP current and high speed lock acquisition. The R and N return to the original values (the normal mode). The frequency division ratio remains the same. <IMAGE></p> |
