| 摘要 |
PURPOSE: An apparatus for generating a line lock clock signal is provided to minimize an error quantity accumulated at PLL by generating a window signal for making noise and phase error not eliminated in a period where a field is changed, and to prevent an upper part of a screen against VCR output image screen from being bent by generating a line lock clock signal synchronized to a horizontal synchronous signal of an image signal during a vertical blanking period. CONSTITUTION: In an apparatus for generating a line lock clock signal, a synchronous separator(41) receives an image signal, and divides only a synchronization of the image signal. A noise and phase error eliminating part(43) receives an output signal from the synchronous separator and a line lock clock signal, and outputs the output signal from the synchronous separator against predetermined lines where a field is changed. A noise comprised in the output signal from the synchronous separator is eliminated corresponding to the line lock clock signal in a line of the image signal inputted after the predetermined lines. The noise and phase error eliminating part(43) outputs a phase locked loop reference signal having the same period as a horizontal synchronous signal of the image signal. A phase locked synchronous loop(50) receives the PLL reference signal as a reference signal and an N-divided line lock clock signal and outputs the line lock clock signal synchronized with the PLL reference signal.
|
