| 摘要 |
PURPOSE: A controller for a 12C bus(inter-integrated circuit serial interface bus) is provided to improve the speed of data transmission, as each device processes transmitting/receiving data during the next cycle process, without pulling down a SCI(Serial Clock Line). CONSTITUTION: A bus controller for a 12C bus(inter-integrated circuit serial interface bus) comprises a first buffer, a second buffer, a shift register, a clock controlling section, and a flag register. The first buffer stores transmission data, and the second buffer stores reception data. The shift register receives serial data, which is transmitted by receiving parallel transmission data from the first buffer when transmitting the data, and outputs the reception data to the second buffer. The clock controlling section inputs a clock signal from a clock transmission line of the 12C bus when receiving data, provides a shift clock signal to the shift register, and outputs the clock signal to the clock transmission line of the 12C bus when transmitting the data. The flag register is set when the transmission data is loaded to the first transmission buffer, and is reset, as the data stored in the first transmission buffer is inputted to the shift register.
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