| 摘要 |
PURPOSE: A tone delivery circuit is provided to control tone data by a constant intermittent rate to store the tone data and the intermittent rate data at different regions by use of a memory of a small capacity. CONSTITUTION: The tone delivery circuit comprises: a memory (100) which stores tone data and intermittent rate data; and a counter logic (200) which reads the tone data from the memory to transfer loading the read tone data on a corresponding time slot and reads the intermittent rate data every predetermined time so as to control different intermittent rates with regard to tones. The counter logic (200) includes a clock generator (202) for generating a predetermined clock, an address bus selector (206) for selecting an address bus, an address generator (204) for receiving the clock signal to generate an address for reading tone data and cadence control data on the selected address bus, and a pattern generator (208) inserted into a corresponding time slot during a cadence off time for generating a pattern.
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