MEMORY LOGIC COMPLEX INTEGRATED CIRCUIT APPARATUS HAVING DRAM AND BUFFER MEMORY AND ERROR DETECTION METHOD OF DRAM

摘要

PURPOSE: A memory logic complex integrated circuit apparatus having a dynamic random access memory(DRAM) and a buffer memory is provided to detect an error of the DRAM under the normal operation. CONSTITUTION: The memory logic complex integrated circuit apparatus having a dynamic random access memory(DRAM) and a buffer memory comprises: a data input/output part(111); a data extension part(121); a built in self test(BIST) circuit(131); the first to the third selection part(143); a buffer memory(151), a dynamic random access memory(DRAM)(161); a logic circuit(171); an output control part(181); and a selection control part(191). Thereby, it is possible to reduce the magnitude of the memory logic complex integrated circuit apparatus and to know exactly the operation speed of the DRAM under the normal operation.