| 摘要 |
<p>PROBLEM TO BE SOLVED: To provide a semiconductor storage for preventing the delay in access to a memory cell and erroneous writing within a range from a high power supply voltage to a low power supply voltage. SOLUTION: A word line enable signal WLE that is generated by a timing generator TG surely reaching an L level for a specific period regardless of a power supply voltage. A column address signal RAD that is delayed by a delay circuit BDL in a column address buffer RAB changes in a period when the word line enable signal WLE is at an L level.</p> |
