| 摘要 |
PROBLEM TO BE SOLVED: To provide a small memory in which data can be read out and written simultaneously. SOLUTION: In a DRAM chip, a memory cell array 5 which comprises a memory cell specified by a row address and a column address is provided. In addition, a row decoder 3R which specifies memory cells in a prescribed row so as to correspond to the row address is provided. In addition, a column switch 7i and a column switch 107i as a plurality of switch means which are arranged in parallel so that the memory cells corresponding to the column address out of memory cells corresponding to the row address are set to a state that data can be read out and written are provided. When two column addresses W, R are given, a column switch 7W and a column switch 107R are controlled in such a way that the memory cells corresponding to the column address W and the column address R out of the memory cells corresponding to the row address are set to a state that data can be read out and written.
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