| 摘要 |
A sequential logic circuit having a series of data signal bistable elements is described. Each data signal bistable element is clocked by a corresponding qualified clock. The qualified clocks are generated by a series of AND gates that each have one input coupled to a global clock and the other input coupled to a valid signal such that the data signal bistable element is only clocked when valid data is present. A series of valid signal bistable elements, one for each data signal bistable element, are used to provide the valid signal to each AND gate. Since the data signal bistable elements are clocked only when valid data is present instead of continuously, the invention provides for a significant reduction in the power consumption of the sequential logic circuit.
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