发明名称 Multiprocessor system with partial broadcast capability of a cache coherent processing request
摘要 Information indicative of whether each processor unit caches data which belongs to each of the plural areas of the main memory larger than a cache line is stored in the multicast table. The destinations of a coherent processing request which should be sent to other processor units are limited by the information stored in this table. The interconnection network broadcasts the request to the limited destinations. When the processor unit of the destination of this processing request sends back a cache status of the data designated by the request, it also sends back the caching status in the processor unit concerning a specific memory area which includes the data. Depending on this send back, the request source processor unit renews a portion relating to the destination processor unit within the caching status concerning that specific memory area stored in the processor unit.
申请公布号 US6038644(A) 申请公布日期 2000.03.14
申请号 US19970820831 申请日期 1997.03.19
申请人 HITACHI, LTD. 发明人 IRIE, NAOHIKO;HAMANAKA, NAOKI;SHIBATA, MASABUMI
分类号 G06F12/08;(IPC1-7):G06F12/12 主分类号 G06F12/08
代理机构 代理人
主权项
地址