| 摘要 |
A method of patterning a polysilicon gate using an oxide hard mask using a novel 4 step insitu etch process. All 4 etch steps are performed insitu in a polysilicon high density plasma (TCP-transformer coupled plasma) etcher. A multi-layered semiconductor structure 35 (FIG. 1) is formed comprising: a substrate 10, a gate oxide layer 14, a polysilicon layer 18, a hard mask layer 22, and a bottom anti-reflective coating (BARC) layer 26 and a resist layer 30. The 4 step insitu etch process comprises: a) in STEP 1, etching the bottom anti-reflective coating (BARC) layer by flowing HBr and O2 gasses, and applying a first TCP Power and a first Bias power; b) in STEP 2, etching the hard mask by flowing a flouorocarbon gas; and applying a second TCP Power and second Bias power; c) in STEP 3-stripping the bottom anti-reflective coating (BARC) layer by flowing oxygen and applying a third TCP Power and a third Bias power; d) in STEP 4-etching the polysilicon layer by flowing chlorine species, oxygen species; Helium species and bromine gas species and applying a fourth TCP Power and a fourth Bias power.
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