发明名称 |
CLOCK ADAPTER USING A PHASE LOCKED LOOP CONFIGURED AS A FREQUENCY MULTIPLIER WITH A NON-INTEGER FEEDBACK DIVIDER |
摘要 |
A phase locked loop configured as a frequency multiplier capable of nonintegral feedback path division utilizes a multiphase voltage controlled oscillator (5) which generates plurality of signals (10a - 10f) having a substantially identical frequency but each offset equally from the other by a given phase angle. A commutator (3) selects signals of adjacent phases so as to give the time average output signal (9) a frequency higher of lower than the frequency 10a - 10f. Frequency translation is accomplished by periodically selecting signals having a longer or shorter period as desired so that a clock output signal is delayed or advanced by an appropriate amount. In the preferred embodiment, the clock adapter is capable of converting a 1.544 MHz signal to a 2.048 MHz signal or vice versa.
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申请公布号 |
CA2002382(C) |
申请公布日期 |
2000.03.14 |
申请号 |
CA19892002382 |
申请日期 |
1989.11.07 |
申请人 |
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发明人 |
JENNINGSCHECK, WILLIAM STEPHEN |
分类号 |
H03L7/18;(IPC1-7):H03L7/18 |
主分类号 |
H03L7/18 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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